dual p - channel logic level enhancement mode field effect transistor p06b03lv g sop - 8 lead free niko - sem 1 may - 0 4 - 200 5 absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol limits units drain - source voltage v d s - 30 v gate - source voltage v gs 20 v t c = 25 c - 6 continuous drain current t c = 70 c i d - 5 pulsed drain current 1 i dm - 30 a t c = 25 c 2.5 power dissipation t c = 70 c p d 1 .3 w operating junction & storage temperature range t j , t stg - 55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction - to - ambient r q ja 62.5 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1 % electrical characteristics (t c = 25 c , unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain - source breakdown voltage v (b r)dss v gs = 0v, i d = - 250 m a - 30 gate threshold voltage v gs(th) v ds = v gs , i d = - 250 m a - 0.9 - 1.5 - 3 v gate - body leakage i gss v ds = 0v, v gs = 20v 100 na v ds = - 24v, v gs = 0v 1 zero gate voltage drain current i dss v ds = - 20v, v gs = 0v, t j = 125 c 10 m a on - state drain current 1 i d(on) v ds = - 5v, v gs = - 10v - 30 a v gs = - 4.5v, i d = - 5a 65 80 drain - source on - state resistance 1 r ds(on) v gs = - 10v, i d = - 6a 40 50 m [ g :gate d :drain s :source product summary v (br)dss r ds(on) i d - 30 50m [ - 6a
dual p - channel logic level enhancement mode field effect transistor p06b03lv g sop - 8 lead free niko - sem 2 may - 0 4 - 200 5 forward transconductance 1 g fs v ds = - 10v, i d = - 6a 16 s dynamic inpu t capacitance c iss 530 output capacitance c oss 135 reverse transfer capacitance c rss v gs = 0v, v ds = - 15v, f = 1mhz 70 pf total gate charge 2 q g 10 14 gate - source charge 2 q gs 2.2 gate - drain charge 2 q gd v ds = 0.5v (br)dss , v gs = - 10v, i d = - 6a 2 nc turn - on delay time 2 t d(on) 5.7 rise time 2 t r v ds = - 15v, r l = 1 [ 10 turn - off delay time 2 t d(off) i d @ - 1a, v gs = - 10v, r gs = 6 [ 18 fall time 2 t f 5 ns source - drain diode ratings and characteristics (t c = 25 c) continuous current i s - 2.1 pulsed current 3 i sm - 4 a forward voltage 1 v sd i f = - 1a, v gs = 0v - 1.2 v reverse recovery time t rr i f = - 5a, dl f /dt = 100a / m s 15.5 ns reverse recovery charge q rr 7.9 nc 1 pulse test : pulse width 300 m sec, duty cycle 2 h . 2 independent of operating temperature. 3 pulse width limited by maximum junction te mperature. remark: the product marked with ?p06b03lv g ?, date code or lot # orders for parts with lead - free plating can be placed using the pxxxxxxg parts name.
dual p - channel logic level enhancement mode field effect transistor p06b03lv g sop - 8 lead free niko - sem 3 may - 0 4 - 200 5 typical characteristics
dual p - channel logic level enhancement mode field effect transistor p06b03lv g sop - 8 lead free niko - sem 4 may - 0 4 - 200 5
dual p - channel logic level enhancement mode field effect transistor p06b03lv g sop - 8 lead free niko - sem 5 may - 0 4 - 200 5 soic - 8 (d) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 4.8 4.9 5.0 h 0.5 0.715 0.83 b 3.8 3.9 4.0 i 0.18 0.254 0.25 c 5.8 6.0 6.2 j 0.22 d 0.38 0.445 0.51 k 0 4 8 e 1.27 l f 1.35 1.55 1.75 m g 0.1 0.175 0.25 n
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